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h 622 mbps multimode fiber transceiver for atm, sonet sts-12/sdh stm-4 technical data features ? 1300 nm led-based transceiver for 500 m links with mmf cables ? compliant with atm forum 622.08 mbps physical layer specification af-phy-0046.000 ? compliant with specifica- tions proposed to ansi t1e1.2 committee for inclusion in t1.646-1995 broadband isdn and t1e1.2/ 96-002 sonet network to customer installation interface standards ? compliant with specifications proposed to ansi t1x1.5 committee for inclusion in t1.105.06 sonet physical layer specifications standard ? multisourced 2 x 9 pin- out package style derived from 1 x 9 pin-out industry standard package style ? integral duplex sc connector receptacle compliant with tia/eia and iec standards ? single +5 v power supply operation and pecl logic interfaces ? integral digital pll provides regenerated differential clock output ? integral decision circuit provides re-timed differential data output ? optional internally generated receiver clock ?wave solder and aqueous wash process compatible ? manufactured in an iso 9001 certified facility applications ? atm 622 mbps mmf links from switch-to-switch or switch-to-server in the end-user premise ? sonet sts-12/sdh stm-4 mmf interconnections description general the HFBR-5207 is a 1300 nm led-based transceiver with integral clock and data recovery circuits. it provides a very cost- effective solution to 500 metre 622 mbps data link requirements in the customer premise atm and telecom office markets. the HFBR-5207 provides a low- cost 622 mbps multimode fiber HFBR-5207 (mmf) interconnection for atm switch-to-switch and switch-to- server applications within a customer premise. the HFBR-5207 also provides a low-cost alternative to traditional 1300 nm laser-based, single-mode fiber transmitter/receiver solutions for sonet/sdh connections up to 500 metres long within telecommunication systems. the new multisourced 2 x 9 footprint package style is a variation of the standard 1 x 9 package with an integral duplex sc connector receptacle. the extra row of 9 pins provides connections for the additional recovered clock output as well as an option to generate a local clock from an external, low- frequency reference clock to replace the recovered clock when in-coming optical signals become unusable.
2 single mode transceiver this new 2 x 9 package style also is available in a single mode fiber transceiver version, the cdx2622, with 15 km performance. this single mode product uses the same pin-out so that a single board layout can be designed to provide either multimode or single mode fiber performance depending on which transceiver is inserted. in addition to the integral clock and data recovery circuit, the cdx2622 also provides the traditional tele- com laser diode bias current and output power monitors as well as a transmitter disable function. transmitter section the transmitter section of this transceiver is similar to 1300 nm led transceivers in use at the 155 mbps rate. it consists of a 1300 nm ingaasp led in an optical sub-assembly (osa) which mates to the fiber cable. the led osa is driven by a figure 1. relative timing relationship between output re-timed data and recovered clock signals. signal detect electrical subassembly clock & data recovery and post amplifier ic led driver ic top view pin photodiode duplex sc receptacle led pre- amplifier ic retimed data 2 data 2 optical sub- assemblies recovered clock 2 reference clock lock-to-reference block diagram. custom, silicon bipolar ic which converts differential input pecl logic signals, ecl referenced to a +5 volt sup ply, into an analog led drive current. receiver section the receiver section of the transceiver provides a full set of features including an integral clock and data recovery (cdr) circuit together with an optional, selectable receiver local clock source. the receiver starts with an ingaas pin photo-diode mounted together with a custom, silicon bipolar transimpedance pre- amplifier ic in an osa. this osa is connected to a custom, silicon bipolar circuit providing post- amplification and quantization, cdr function, and optical signal detection. the custom, silicon bipolar circuit includes a signal detect circuit which provides a pecl logic-high output upon detection of a usable input optical signal level. signal detect is a basic fiber failure indicator. this signal-ended low- power pecl output is designed to drive a standard pecl input using a 10 k w load instead of the normal 50 w pecl load. detailed description of receiver cdr function in normal operation, the cdr data loop is able to acquire and maintain bit lock without the use of the optional, external reference clock. this loop consists of a pat- ented phase/frequency detector with false-lock protection. the recovered clock is used to re-time the quantizer data output, which completes the full cdr function. baud interval rd rd clk clk v oh v ol v oh v ol v oh v ol v oh v ol clock period
3 the relative timing relationship between the output re-timed data and the recovered clock signals is shown graphically in figure 1. fundamentally, the rising edge of the clock and the falling edge of the clock bar will occur at the center of the data or data-bar baud interval. conversely, the clock falling edge and the clock- bar rising edge will be at the edges of the data or data-bar baud interval. for input optical power greater than the specified receiver sensi- tivity of -26 dbm, the bit-error- ratio will be better than 1 x 10 -10 . as the input power is decreased by several db, the bit-error-ratio degrades. within 1 db below the 1 x 10 -2 ber input optical power level, the cdr will begin to lose lock and the clock frequency will drift from 622.08 mhz. once the cdr loses lock, the clock fre- quency will sweep in the entire vco range, about 540 to 700 mhz. the rate of the sweep will depend on the input optical power. the sweep rate gets faster the lower the input optical power is. once the input optical power is 2 db below the lock point, the sweep rate approaches the maximum. at this point the clock and data outputs look no different than the case with no input optical power. there will be a data edge for every clock edge. the data output will consist of randomly switching data bits, i.e., noise. detailed description of receiver signal detect feature as the input optical power is decreased, signal detect will switch from high to low (de-assert point) somewhere between 3 db below sensitivity and the no light input level. as the input optical power is increased from very low levels, signal detect will switch from low to high (assert point) somewhere between 2 db below sensitivity and no input optical power at all. the assert level will be at least 1.0 db higher than the de-assert level. optional local clock generation in applications where the receiver recovered clock frequency is not allowed to drift upon loss of input optical signal, this transceiver has the ability to generate a local clock output by multiplying an optional, external 19.44 mhz reference clock up to the oc-12 (622.08 mhz) rate. this feature is possible because the clock recovery system con- sists of two loops: a data loop which locks onto the incoming optical data stream, and a second reference loop which locks onto the optional external reference clock. this optional feature is initiated by applying a lock-to-reference logic low signal to pin 2 (lck ref-) which switches the loop to the external reference clock and disables the received data outputs. pin 2 (lck ref-) can be driven from the signal detect pin 15 (sd) output or from other logic further upstream in the atm interface which may be monitor- ing the quality of the received data stream. product variations available by special request transceiver without cdr function the hfbr-5208 transceiver is available in the smaller 1 x 9 pin- out package style without integral clock and data recovery functions for those designers who prefer the flexibility of designing with a different partitioning of the physical layer interface. transceiver specified for wide temperature range operation the HFBR-5207 is specified for operation over normal commercial temperature range of 0 c to 70 c. the product has been character- ized and is available with guaran- teed performance over wider temperature ranges by special request. other members of hp 622 mb/s product family ? hfbr-5208, 1300 nm led- based transceiver in 1 x 9 package for 500 m links with mmf cables ? cdx2622, 1300 nm laser-based transceiver with integral clock and data recovery in 2 x 9 package for links with smf cables ? xmt5360-622, 1300 nm laser- based transmitter in pigtailed package for 2 km and 15 km links with smf cables ? xmt5160-622, 1300 nm laser- based transmitter in pigtailed package for 40 km links with smf cables ? rcv1201d-622, receiver in pigtailed package for 2 km, 15 km and 40 km links with smf cables ? rgr1622, receiver with integral clock and data recovery in pigtailed packages for 2 km, 15 km and 40 km links with smf cables ? hp is planning to have a compatible smf 1x9 solution available. please contact your hp field sales representative for additional information.
4 applications information typical ber performance of receiver versus input optical power level the HFBR-5207 transceiver can be operated at bit-error-ratio conditions other than the required ber = 1 x 10 -10 of the 622 mbd atm forum 622.08 mbps phys- ical layer standard. the typical trade-off of ber versus relative input optical power is shown in figure 2. the relative input optical power in db is referenced to the input optical power para- meter value in the receiver optical characteristics table. for better ber condition than 1 x 10 -10 , more input signal is needed (+db). for example, to operate the HFBR-5207 at a ber of 1 x 10 -12 , the receiver will require an input signal approximately 0.6 db higher than the -26 dbm level required for 1 x 10 -10 operation, i.e. -25.4 dbm. recommended circuit schematic when designing the HFBR-5207 circuit interface, there are a few fundamental guidelines to follow. for example, in the recommended circuit schematic, figure 3, the differential data lines should be treated as 50 ohm microstrip or stripline transmission lines. this will help to minimize the parasitic inductance and capacitance effects. proper termination of the differ- ential data and clock signals will prevent reflections and ringing which would compromise the sig- nal fidelity and generate unwanted electrical noise. locate termination at the received signal end of the transmission line. the length of these lines should be kept short and of equal length to prevent pulse-width distortion and data- to-clock timing skew from occur- ring. for the high-speed signal figure 2. relative input optical power C dbm avg. lines, differential signals should be used, not single-ended signals. these differential signals need to be loaded symmetrically to prevent unbalanced currents from flowing which will cause distor- tion in the signal. maintain a solid, low inductance ground plane for returning signal currents to the power supply. multi-layer plane printed circuit board is best for distribution of v cc , returning ground currents, forming transmission lines and shielding. also, it is important to suppress noise from influencing the fiber-optic transceiver per- formance, especially the receiver and the clock recovery circuits. proper power supply filtering of v cc for this transceiver is accom- plished by using the recom- mended, separate filter circuits shown in the recommended circuit schematic figure for the transmitter and receiver sections. these filter circuits suppress v cc noise of 50 mv peak-to-peak or less over a broad frequency range. this prevents receiver sensitivity degradation as well as false-lock or loss-of-lock in the clock recovery circuitry due to v cc noise. it is recommended that surface-mount components be used. use tantalum capacitors for the 10 m f capacitors and mono- lithic, ceramic bypass capacitors for the 0.1 m f capacitors. also, it is recommended that a surface- mount coil inductor of 1 m h be used. ferrite beads can be used to replace the coil inductors when using quieter v cc supplies, but a coil inductor is recom- mended over a ferrite bead. coils with a low, series dc resistance (<0.7 ohms) and high, self- resonating frequency are recom- mended. all power supply components need to be placed physically next to the v cc pins of the receiver and transmitter. use a good, uni form ground plane with a minimum number of holes to provide a low-inductance ground current return path for the power supply currents. in addition to these recommenda- tions, hewlett-packards applica- tion engineering staff is available for consulting on best layout practices with various vendors mux/demux, clock generator and clock recovery circuits. hp has participated in several reference design studies and is prepared to share the findings of these studies with interested customers. contact your local hp sales representative to arrange for this service. bit error ratio -5 3 10 -2 relative input optical power ?dbm avg. -3 1 -2 0 10 -4 10 -6 10 -8 10 -10 10 -11 10 -12 10 -7 10 -5 10 -3 -4 -1 2 10 -9 10 -13 10 -14 10 -15 linear extrapolation of 10 -4 through 10 -7 data actual data
5 figure 3. recommended circuit schematic. locate filter at v cc pins r7 r6 r8 v cc c3 c4 l1 l2 c1 c2 r15 r1 r4 c5 r3 r2 v cc terminate at fiber-optic transceiver inputs terminate at phy device inputs c8 r12 r10 r9 r14 c7 r11 r13 v cc clk clk r5 c6 1 ref clk 2 lck ref 3 clk 4 clk 5* nic 6* nic 7* nic 8* nic 9* nic 18 17 rd 16 rd 15 sd 14 13 12 td 11 td 10 rx v ee rx v cc tx v cc tx v ee terminate at clock inputs ref clk HFBR-5207 top view nic notes: the split-load terminations for pecl signals need to be located at the input of devices receiving those pecl signals. r1 = r4 = r6 = r8 = r10 = r12 = r14 = 130 w . r2 = r3 = r5 = r7 = r9 = r11 = r13 = 82 w . c1 = c2 = c3 = c5 = c6 = c7 = 0.1 ?. c4 = c8 = 10 ?. l1 = l2 = 1 ? coil. r15 = 10 k w . nic = no internal connection * for this multimode HFBR-5207 transceiver, pins 5-9 are not used. for the single-mode cdx2622 transceiver, pins 5-9 are used for laser diode bias and optical power monitoring as well as to provide a transmitter disable function. optional rd rd sd v cc td td rx tx nic
6 figure 4. recommended board layout hole pattern evaluation circuit boards evaluation circuit boards imple- menting this recommended circuit design are available from hewlett- packards application engineering staff. contact your local hp sales representative to arrange for access to one if needed. operation in -5.2 v designs for applications that require -5.2 vdc power supply level for true ecl logic circuits, the HFBR-5207 transceiver can be operated with a v cc = 0 vdc and a v ee = -5.2 vdc. this transceiver is not specified with an operating, negative power supply voltage. the potential compromises that can occur with use of -5.2 vdc power are that the absolute volt- age states for v oh and v ol will be changed slightly due to the 0.2 v difference in supply levels. also, noise immunity may be compro- mised for the HFBR-5207 trans- ceiver because the ground plane is now the v cc supply point. the suggested power supply filter circuit shown in the recommended circuit schematic figure should be located in the v ee paths at the transceiver supply pins. direct coupling of the differential data and clock signals can be done between the HFBR-5207 trans- ceiver and the standard ecl circuits. for guaranteed -5.2 vdc operation, contact our local hewlett-packard component field sales engineer for assistance. recommended solder and wash process the HFBR-5207 is compatible with industry-standard wave or hand solder processes. (8x) 2.54 0.100 33.02 1.300 20.32 0.800 1.9 ?0.1 0.075 ?0.004 (2x) 0 00 ma 0.8 ?0.1 0.031 ?0.004 (18x) 0 00 ma ? top view 2.54 0.100 hfbr-5200 process plug the HFBR-5207 transceiver is supplied with a process plug, the hfbr-5200, for protection of the optical ports with the duplex sc connector receptacle. this process plug prevents contami- nation during wave solder and aqueous rinse as well as during handling, shipping or storage. it is made of high-temperature, molded, sealing material that will withstand 80 c and a rinse pressure of 50 lb/in 2 . recommended solder fluxes and cleaning/degreasing chemicals solder fluxes used with the HFBR-5207 fiber-optic trans- ceiver should be water-soluble, organic solder fluxes. some recommended solder fluxes are lonco 3355-11 from london chemical west, inc. of burbank, ca, and 100 flux from alpha- metals of jersey city, nj. recommended cleaning and degreasing chemicals for the HFBR-5207 are alcohols (methyl, isopropyl, isobutyl), aliphatics (hexane, heptane) and other chemicals, such as soap solution or naphtha. do not use partially halogenated hydrocarbons for cleaning/degreasing. examples of chemicals to avoid are 1,1.1 trichloroethane, ketones (such as mek), acetone, chloroform, ethyl acetate, methylene dichloride, phenol, methylene chloride or n- methylpyrolldone.
7 52.02 (2.048) max. area reserved for process plug 12.70 (0.500) 25.40 (1.000) max. 12.70 (0.500) 11.1 (0.437) max. 3.30 (0.130) 18.57 (0.731) 4.19 (0.165) 20.32 (0.800) 23.55 (0.927) 16.70 (0.657) 17.32 (0.682) 20.32 (0.800) 23.32 (0.918) 0.46 (0.018) note 1 (18x) 2.54 (0.100) 33.02 (1.300) 15.88 (0.625) note 1: solder posts and electrical pins are tin/lead plated. dimensions are in millimeters (inches). HFBR-5207 package outline 0.75 (0.030) ref. 10.35 (0.407) max. 3.12 (0.123) ref. 1.27 (0.050) note 1 (2x) 2.54 (0.100) typ. 8 pls hfbr-5xxx date code (yyww) singapore figure 5. package outline drawing and pinout 18 = v eer 17 = rd+ 16 = rd 15 = sd 14 = v ccr 13 = v cct 12 = td 11 = td+ 10 = v eet top view nic nic 1 = ref clk 2 = lck ref 3 = clk 4 = clk+ 5 = nic 6 = nic 7 = nic 8 = nic 9 = nic rx tx nic = no internal connection
8 shielding. performance of a sys- tem containing these transceivers within a well designed chassis is expected to be better than the results of these tests with no chassis enclosure. immunity equipment utilizing these HFBR-5207 transceivers will be subject to radio-frequency electromagnetic fields in some environments. these transceivers, with their integral shields, have been characterized without the benefit of a normal equipment chassis enclosure and the results are reported below. performance of a system containing these transceivers within a well- designed chassis is expected to be better than the results of these tests without a chassis enclosure. the second case to consider is static discharges to the exte- rior of the equipment chassis containing the transceiver parts. to the extent that the duplex sc connector receptacle is exposed to the outside of the equipment chassis, it may be subject to whatever esd system level test criteria that the equipment is intended to meet. electromagnetic interference (emi) most equipment designs utilizing these high-speed transceivers from hewlett-packard will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. the HFBR-5207 emi has been characterized without a chassis enclosure to demonstrate the robustness of the parts integral regulatory compliance these transceiver products are intended to enable commercial system designers to develop equipment that complies with the various regulations governing certification of information technology equipment. see the regulatory compliance table for details. additional information is available from your hewlett- packard sales representative. electrostatic discharge (esd) there are two design cases in which immunity to esd damage is important. the first case is during handling of the transceiver prior to mount- ing it on the circuit board. it is important to use normal esd handling precautions for esd sensitive devices. these precau- tions include using grounded wrist straps, work benches, and floor mats in esd controlled areas.
9 regulatory compliance C typical performance feature test method performance electrostatic discharge mil-std-883c class 1 (>1000 volts) (esd) to the electrical method 3015.4 pins electrostatic discharge variation of typically withstand at least 25 kv without damage (esd) to the duplex sc iec 801-2 when the duplex sc connector receptacle receptacle is contacted by a human body model probe. electromagnetic fcc class b typically provide a 4 db margin to fcc class b interference (emi) cenelec en55022 and a 1 db margin to the other noted standard class b (cispr 22b) limits when tested at a certified test range with the vcci class 2 transceiver mounted to a circuit card without a chassis enclosure at frequencies up to 1 ghz. margins above 1 ghz are dependent on customer board and chassis designs. immunity variation of iec 801-3 typically show no measurable effect from a 3 v/m field swept from 10 to 450 mhz applied to the transceiver when mounted to a circuit card without a chassis enclosure. the HFBR-5207 led transmitters are classified as iec 825-1 accessible emission limit (ael) class 1 based upon the current proposed draft scheduled to go into effect on january 1, 1997. ael class 1 led devices are considered eye safe.
10 absolute maximum ratings parameter symbol min. typ. max. unit reference storage temperature t s -40 85 c lead soldering temperature t sold 260 c lead soldering time t sold 10 sec. supply voltage v cc -0.5 7.0 v data input voltage v i -0.5 v cc v transmitter v d 1.6 v note 1 differential input voltage output current i o 50 ma relative humidity rh 0 95 % recommended operating conditions parameter symbol min. typ. max. unit reference ambient operating temperature t a 070 c supply voltage v cc 4.75 5.25 v power supply rejection psr 50 mv p-p note 2 transmitter data input v il -v cc -1.810 -1.475 v note 3 voltage-low transmitter data input v ih -v cc -1.165 -0.880 v note 3 voltage-high transmitter differential v d 0.3 1.6 v input voltage receiver lck ref- & ref clk v il -v cc -1.950 -1.620 v note 3 single-ended input voltage-low receiver lck ref- & ref clk v ih -v cc -1.045 -0.740 v note 3 single-ended input voltage-high clock and data output load r cl /r dl 50 w note 4 signal detect output load r sdl 710 k w note 5 notes : 1. this is the maximum voltage that can be applied across the differential transmitter data inputs without damaging the esd protection circuit. 2. tested with a 50 mv p-p sinusoidal signal in the frequency range from 500 hz to 450 mhz imposed on the v cc supply with the recommended power supply filter in place, see figure 3. typically less than a 0.25 db change in sensitivity is experienced. 3. compatible with 10k, 10kh and 100k ecl and pecl output signals. 4. the outputs are terminated to v cc - 2 v. 5. the output is terminated to ground.
11 transmitter electrical characteristics (t a = 0 c to 70 c, v cc = 4.75 v to 5.25 v) parameter symbol min. typ. max. unit reference supply current i cct 150 200 ma note 6 power dissipation p dist 0.75 1.05 w data input current-low i il -350 0 m a data input current-high i ih 16 350 m a receiver electrical characteristics (t a = 0 c to 70 c, v cc = 4.75 v to 5.25 v) parameter symbol min. typ. max. unit reference supply current i ccr 225 300 ma power dissipation p disr 1.02 1.49 w note 7 data and clock output v ol -v cc -1.950 -1.620 v note 8 voltage-low data and clock output v oh -v cc -1.045 -0.740 v note 8 voltage-high data and clock output t r 0.2 0.3 0.51 ns note 9 rise ti9 data and clock output t f 0.2 0.3 0.51 ns note 9 fall time signal detect output v ol -v cc -1.950 -1.620 v note 8 voltage-low (de-asserted) signal detect output v oh -v cc -1.045 -0.740 v note 8 voltage-high (asserted) signal detect assert time t sda 100 m s note 10 (off to on) signal detect de-asserted time t sdd 100 m s note 11 (on to off) ref clk & lck ref-input i il -500 -20 m a current-low ref clk & lck ref-input i ih 80 500 m a current-high notes : 6. the i cc value is held nearly constant to minimize unwanted electrical noise from being generated and conducted or emitted into neighboring circuitry. 7. power dissipation value is the power dissipated in the receiver itself. it is calculated as the sum of the products of v cc and i cc minus the sum of the products of the output voltages and load currents. 8. these outputs are compatible with 10k, 10kh and 100k ecl and pecl inputs. 9. these are 20% - 80% values. 10. the signal detect output will change from logic 0 to 1 within 100 m s of a step transition in input optical power from no light to - 26 dbm avg. 11. the signal detect output will change from logic 1 to 0 within 100 m s of a step transition in input optical power from -28 dbm avg. to no light.
12 transmitter optical characteristics (t a = 0 c to 70 c, v cc = 4.75 v to 5.25 v) parameter symbol min. typ. max. unit reference output optical power p o (bol) -19 -14 dbm avg. 62.5/125 m m, na = 0.275 fiber p o (eol) -20 -14 output optical power p o (bol) -21.5 -14 dbm avg. 50/125 m m, na = 0.20 fiber p o (eol) -22.5 -14 output optical power at p o (o) -60 dbm avg. logic 0 state optical extinction ratio 10 46 db center wavelength l c 1270 1330 1380 nm spectral width-fwhm s 136 200 nm optical rise/fall times t r /t f 0.9 1.25 ns note 12 overshoot 25 % systematic jitter contributed sj 0.04 0.23 ns p-p note 13 by the transmitter random jitter contributed by rj 0.0 0.10 ns p-p note 14 the transmitter receiver optical characteristics (t a = 0 c to 70 c, v cc = 4.75 v to 5.25 v) parameter symbol min. typ. max. unit reference input optical power p in -26 -14 dbm avg. note 15 input optical wavelength l 1270 1380 nm output static clock/data saj c/d -120 25 120 ps alignment jitter output clock random jitter rj c 60 110 ps p-p signal detect-asserted p a p d +1.0 db -28 dbm avg. signal detect-de-asserted p d -45 dbm avg. signal detect-hysteresis p a - p d 1.0 db notes : 12. these are 10-90% values. 13. this contributed jitter allows the incoming data signal to contribute additional jitter without violating the 0.4 ns maximum allowed optical output systematic jitter per the atm forum specification for this mmf interface. 14. this contributed jitter allows the incoming data signal to contribute additional jitter without violating the 0.15 ns maximum allowed optical output random jitter per the atm forum specification for this mmf interface. 15. the sensitivity is provided at a ber of 1 x 10 -10 or better with an input signal consisting of 622.08 mb/s, 2 23 - 1 prbs pattern sections with 72 1s and 72 0s inserted per itu-t g.958 appendix i. the transmitter is operating at the 622.08 mb/s rate during the test to simulate any cross-talk effects between the transmitter and receiver sections of the transceiver. the output signal is re-timed data.
13 table 1. pin out table pin symbol functional description mounting studs the mounting studs are provided for transceiver mechanical attachment to the circuit board. they are embedded in the non-conductive plastic housing and are not connected to the transceiver internal circuit. they should be soldered into plated-through holes on the printed circuit board. 1 ref clk reference clock - optional feature reference clock can be used as an optional, internally generated local receiver clock when the input optical signal is disrupted. see pin 2 lck ref-description. this input is not required for the normal operation of the clock recovery circuit. this is a single- ended pecl input. if this reference clock input is used, provide a 19.44 mhz external reference clock signal and terminate at this input pin with standard pecl techniques. if this reference clock input is not used, leave the input open-circuited. with the input open-circuited, an internal pull-down resistor will bias this input to a low-state condition. 2 lck ref- lock-to-reference clock bar - optional feature lock-to-reference clock bar can be used to help manage the performance of the receiver when the input optical signal is disrupted. when used, it places the received data outputs in static states and it triggers an internally generated local receiver clock to be output on clk/clk- in substitution of recovered clock. this is a single-ended pecl input. for normal operation of the transceiver, connect this lock-to-reference-bar input to v cc or a pecl high-state (v ih ) which causes the internal cdr circuit to output recovered differential clock on clk/clk- and re-timed differential data on rd/rd-. for optional use to make static the received data outputs and to output the internally generated local receiver clock, connect lck ref- input to a pecl low-state (v il ), or leave this input open-circuited. when this is done it will cause: 1) the received data outputs to change to static pecl logic levels (rd = v ol and rd- = v oh ), 2) the internal cdr circuit to switch over to using the external reference clock, if provided, as the timing source to generate a 622.08 mb/s clock output on clk/clk-. if the feature is used, one way to implement it is to connect this pin to signal detect directly with a single pull-down resistor of 10 k w to ground. if this lock-to-reference feature is not used, this pin must be connected directly to v cc or a pecl high-state to disable it. 3 clk- received recovered clock out bar see pins 1 & 2 for optional, local generated clock output. the rising edge occurs coincident with the edges of the received data output. the falling edge occurs in the middle of the received data baud period. terminate this high-speed, complementary, differential clock output with standard pecl techniques at the clock input point of the follow-on device. if this clock output is not used, leave it open-circuited with no printed circuit board trace attached to this output pin.
14 table 1. pin out table (continued) pin symbol functional description 4 clk+ received recovered clock out see pins 1 & 2 for optional, local generated clock output. the falling edge occurs coincident with the edges of the received data output. the rising edge occurs in the middle of the received data baud period. terminate this high-speed, complementary, differential clock output with standard pecl techniques at the clock input point of the follow-on device. if this clock output is not used, leave it open-circuited with no printed circuit board trace attached to this output pin. 5 nic pins 5 through 9 are not connected to the transceiver internal circuit. they are reserved 6 nic for use with the complementary hewlett-packard cdx2622 single mode fiber-optic 7 nic transceiver which is provided in the same 2 x 9 package style. see the hewlett-packard 8 nic cdx2622 data sheet for full details on the use of these pins. 9 nic 10 veet transmitter signal ground directly connect this pin to the transmitter signal ground plane. 11 td+ transmitter data in terminate this high-speed, differential transmitter data bar input with standard pecl techniques at the transmitter input pin. 12 td- transmitter data in bar terminate this high-speed, differential transmitter data input with standard pecl techniques at the transmitter input pin. 13 v cct transmitter power supply provide +5 vdc via the recommended transmitter power supply filter circuit. locate the power supply filter circuit as close as possible to the v cct pin. 14 v ccr receiver power supply provide +5 vdc via the recommended receiver power supply filter circuit. locate the power supply filter circuit as close as possible to the v ccr pin. 15 sd signal detect normal input optical power levels to the receiver result in a logic 1 output (asserted). low input optical power levels to the receiver result in a fault indication shown by a logic 0 output (de-asserted). signal detect is a single-ended, low-power, pecl output. since sd is a low-power pecl output, complete the interconnection of sd output with other pecl inputs using a 10 k w pull-down resistor to v ee to allow biasing of this interconnection. do not load this sd output with standard pecl, 50 w to vcc-2v, termination. if signal detect output is not used, leave it open-circuited. this signal detect output can be used to drive a pecl input on an upstream circuit, such as, signal detect input, loss of signal-bar input, or to optionally drive the lock- to-reference-bar input (pin 2) of this transceiver.
15 table 1. pin out table (continued) pin symbol functional description 16 rd- re-timed receiver data out bar terminate this high-speed, differential, pecl output with standard pecl techniques at the follow-on device input pin. 17 rd+ re-timed receiver data out terminate this high-speed, differential, pecl output with standard pecl techniques at the follow-on device input pin. 18 v eer receiver signal ground directly connect this pin to receiver signal ground plane.
for technical assistance or the location of your nearest hewlett-packard sales office, distributor or representative call: americas/canada: 1-800-235-0312 or 408-654-8675 far east/australasia: (65) 290-6305 japan: (81 3) 3335-8152 europe: call your local hp sales office. data subject to change. copyright ? 1996 hewlett-packard co. printed in u.s.a. 5965-1533e (6/96) h

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